How the TRS-80 Color Computer 1, 2 and 3 High-Speed Pokes Function
R1,R0 = CPU RATE REGISTERS
R0 IS CLEARED BY ANY WRITE TO $FFD6 (65494)
R0 IS SET BY ANY WRITE TO $FFD7 (65495)
R1 IS CLEARED BY ANY WRITE TO $FFD8 (65496)
R1 IS SET BY ANY WRITE TO $FFD9 (65497)
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It is important to understand that these are S.A.M. registers, and since the S.A.M. has no data lines connected to it, the actual data written is irrelevant. The S.A.M. registers are simply a series of WRITE ONLY latches or switches. Writing to an even address clears the latch assigned to that address range and writing to an odd address sets the latch assigned to that address range. Each latch occupies two consecutive memory addresses.
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STUDY THE TABLES BELOW FOR MORE DETAILED INFORMATION:
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=TABLE 1 : CPU RATE REGISTER DESCRIPTIONS =
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DECIMAL HEXADECIMAL WRITE HERE TO: REGISTER
65494 $FFD6 CLEAR R0 CPU RATE R0
65495 $FFD7 SET R0 CPU RATE R0
65496 $FFD8 CLEAR R1 CPU RATE R1
65497 $FFD9 SET R1 CPU RATE R1
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*TABLE 2 : CPU RATE REGISTER COMBINATIONS *
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R1 R0 CPU SPEED NOTES
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0 0 .89 Mhz ONLY THIS IS THE NORMAL OPERATING
FREQUENCY OF THE COCO 1,2,3
TDP-100 AND TANO DRAGON.
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0 1 .89 Mhz / 1.78 Mhz CPU SPEED IS ADDRESS DEPENDENT. SEE
TEXT. (THIS IS THE HIGH-SPEED MODE
OF THE COCO 1,2 TDP-100 AND TANO /
DRAGON DATA PRODUCTS "DRAGON").
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1 0 1.78 Mhz ONLY THIS IS THE HIGH-SPEED MODE OF THE
CoCo 3, WHICH OPERATES AT THIS
SPEED 100% OF THE TIME UNDER OS-9
LEVEL 2. SOME LATER MODEL CoCo 2's
COULD OPERATE AT THIS SPEED WITH
LOSS OF VIDEO.
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1 1 UNUSED UNDEFINED STATE.
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THE REGISTER COMBINATIONS ARE MORE FULLY DESCRIBED AS FOLLOWS:
00 = NORMAL OPERATING FREQUENCY OF THE TRS-80 COLOR COMPUTER 1, 2, AND 3 AS WELL AS THE DRAGON DATA PRODUCTS (A.K.A. TANO) DRAGON AND TANDY DATA PRODUCTS TDP-100. THE SYSTEM OPERATES AT .89 Mhz 100% OF THE TIME.
01=CoCo 1 AND 2 HIGH-SPEED POKE (POKE 65495,0). THE SYSTEM RUNS AT .89 Mhz DURING ACCESS TO RAM ADDRESSES ($0000-$7FFF) AND 1.78 Mhz DURING ACCESS TO ROM ADDRESSES ($8000-$FEFF). [NOTE THAT $FF00-$FFFF CONTAINS THE I/O AREA OF THE COCO AND THE RESET AND INTERRUPT VECTORS]. THIS IS WHY THIS MODE IS REFERRED TO AS ADDRESS DEPENDENT. NOTE THAT IF YOU HAVE A 64K RAM SYSTEM, AND IT IS IN THE RAM MODE OR ALL RAM MODE AS IT IS OFTEN CALLED (MEANING THE ROMS HAVE BEEN COPIED TO RAM, AND THE ROMS SWITCHED OUT WITH THE UPPER 32K RAM), THEN THE SYSTEM WILL RUN AT .89 Mhz REGARDLESS OF THE ADDRESSES BEING ACCESSED, SINCE, IN THIS MODE, THE ROM AREA CONTAINS RAM.
10=CoCo 3 HIGH-SPEED POKE (POKE 65497,0). THE SYSTEM RUNS AT 1.78 Mhz 100% OF THE TIME, REGARDLESS OF RAM/ROM ACCESSES OR RAM/ROM MODE. THIS MODE WOULD FUNCTION IN THE LATER MODEL CoCo 2's, WITH LOSS OF VIDEO - THE VIDEO WOULD LOSE SYNC BUT THE SYSTEM WOULD STILL BE RUNNING.
11=NOT USED IN ANY MODEL OF THE COCO.
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HAVING READ THE ABOVE INFORMATION, YOU SHOULD HAVE AN IDEA AS TO WHY THE COCO 1 AND 2 HIGH-SPEED POKE WAS NOT IMPLEMENTED IN THE COCO 3. AS THAT MODE IS ADDRESS DEPENDENT AND REQUIRES THAT THE ROMS BE PRESENT, IT WAS (THIS IS ONLY MY OPINION, BUT SEEMS SOUND) NOT IMPLEMENTED IN THE CoCo 3's G.I.M.E. CHIP DUE TO THE FACT THAT THE COCO 3 WAS DESIGNED TO OPERATE IN THE ALL-RAM MODE. THAT IS, IN FACT, HOW BASIC WAS PATCHED TO ACCESS THE NEW FEATURES OF THE CoCo 3 - THE ROMS WERE COPIED TO RAM AT BOOTUP, SWICTHED OUT WITH THE RAM, AND PATCHED TO ACCESS SUPER EXTENDED COLOR BASIC.
NOTE THAT THE CoCo 3 CAN BE PLACED INTO THE ROM MODE, BUT THE ADDRESS DEPENDENT SPEED STILL DOES NOT FUNCTION (PLUS YOU LOSE ACCESS TO THE SUPER EXTENDED BASIC). THIS IS BECAUSE THE ADDRESS DEPENDENT SPEED WAS NOT IMPLEMENTED IN THE G.I.M.E. IT COULD HAVE BEEN, BUT I AM OF THE OPINION THAT THEY G.I.M.E. DESIGNER PROBABLY NEEDED TO SAVE A FEW LOGIC GATES.
COPYRIGHT -MONDAY, 09 OCTOBER 2006
ROBERT ALLEN TURNERALL RIGHTS RESERVED
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